1. Field of the Invention
This invention relates to the manufacture of integrated circuit (IC) devices, and more particularly to a concave channel MOS transistor and a method of fabrication by self-aligned process technology.
2. Description of the Prior Art
With the continued reduction of the size of semiconductor devices, MOS transistor devices having a short channel configuration are widely utilized, and consequently an important aspect of IC design. However, a device having short channel fabricated by conventional process technology has the following drawbacks: (1) hot carrier effects, (2) high leakage current, and (3) sub threshold voltage, all of which will reduce the lifetime of device. Hence, new techniques have been needed that fabricate devices with a substantially short channel configuration, but without the above mentioned drawbacks.
One prior art device that addresses these problem is the "concave channel" MOS transistor. A field oxide layer is first formed by LOCal Oxidation of Silicon (LOCOS) on a substrate, next the field oxide layer is removed to leave a concave area in the substrate. Then a concave channel is formed on the concave area, which will increase the effective channel length resolving hot carrier, leakage current, and sub threshold problems. Referring to FIGS. 1A to 1D, the process steps of a prior art MOS transistor with concave channel is described in detailed as follows.
First, as shown in FIG. 1A, a LOCOS process is performed. For example, a pad oxide layer 11 and a silicon nitride layer 12 are deposited on a P type silicon substrate 10. The pad oxide layer 11 and the silicon nitride layer 12 are patterned to form an opening 13 by conventional lithography and etching processes. A filed oxide layer 14 is formed on portion of the silicon substrate 10 within the opening 13 by thermal oxidation.
Next, as shown in FIG. 1B, the silicon nitride layer 12 is etched away in a hot phosphoric acid solution. N type impurities, such as arsenic ions, are implanted into silicon substrate 10 to form heavily doped N.sup.+ source/drain areas 15, using the field oxide layer 14 as a mask.
Referring to FIG. 1C, the field oxide layer 14 is removed by etching, so as to leave a concave area in the silicon substrate 10. A gate oxide layer 16 is formed on the bottom of the concave area by thermal oxidation or chemical vapor deposition (CVD). A polysilicon layer 17 is deposited overlying the pad oxide layer 11 and gate oxide layer 16. A photoresist layer 18 is coated and patterned on the surface of polysilicon layer 17 to act as a mask.
Then, as shown in FIG. 1D, those portions of the polysilicon layer 17 not covered by the photoresist layer 18 are removed, preferably by reactive ion etching (RIE). The remaining portion of the polysilicon layer 17 forms a polysilicon gate layer 17a. The pad oxide layer 11 is removed preferably by RIE using the photoresist layer 18 as a mask to expose the heavily doped N.sup.+ source/drain areas 15. Finally, after removing the photoresist layer 18, an insulating layer with metal contact via, such as a borophosphosilicate (BPSG) layer 19, is formed on the silicon substrate 10 completing the fabricating of a prior art MOS transistor.
A concave channel is formed in that portion of the silicon substrate 10 disposed under the polysilicon gate layer 17a and between the heavily doped N.sup.+ source/drain areas 15. Thus the effective channel length of the MOS transistor is increased without increasing device size, which helps to prevent problems due to the hot carrier effect, leakage current, etc., mentioned previously However, two photomasks are used in the prior art technique: one to define the field oxide layer 14 and another is to define the polysilicon gate layer 17a. As the size of devices reduces, it becomes ever more difficult to define patterns precisely by lithographic processes on a non-uniform substrate. Hence there is a need to use as few photomasks as possible in order to simplify device manufacture and realize smaller devices.